Widespread shortages of semiconductors over the last year have caused many people to focus on supply chain resilience, with calls to increase chip manufacturing in the U.S. The U.S. Innovation and Competition Act (USICA), which passed the Senate last June, proposes $52 billion to aid domestic semiconductor production, and is awaiting House action. While the main focus for many people is on growing the domestic share of production of silicon chips, we should not overlook chip packaging – the essential process of encapsulating those chips in order to protect them from damage and make them usable by connecting their circuitry to the outside world. This is an area that is going to be important both for supply chain resiliency as well as to sustain future technological advances in electronics.
Packaging is essential to making semiconductor chips usable
Integrated circuit (IC) chips are produced on silicon wafers in multibillion dollar factories known as “fabs.” The individual chips or “die” are produced in repeating patterns, manufactured in batches on each wafer (and across batches of wafers). A 300 mm wafer (about 12 inches in diameter), the size typically used in the most modern fabs, might carry hundreds of large microprocessor chips, or thousands of tiny controller chips. The production process is segmented into a “front end of the line” (FEOL) phase during which billions of microscopic transistors and other devices are created with patterning and etching processes in the body of the silicon, followed by a “back end of the line” (BEOL) in which a mesh of metal traces is laid down to connect everything. The traces consist of vertical segments called “vias,” which in turn connect horizontal layers of wiring. If you have billions of transistors on a chip (the iPhone 13’s A15 processor has 15 billion), you need many billions of wires to connect them. Each individual die might have several kilometers of wiring in total when stretched out, so we can imagine that the BEOL processes are pretty complex. On the very outer layer of the die (sometimes they will use the back of the die as well as the front), designers put microscopic pads that are used to connect the chip to the outside world.
After the wafer is processed, each of the chips is individually “probed” with a test machine to find out which ones are good. These are cut out and put into packages. A package provides both physical protection for the chip, as well as a means to connect electrical signals to the different circuits in the chip. After a chip is packaged it can be placed on electronic circuit boards in your phone, computer, car, or other devices. Some of these packages have to be designed for extreme environments, like in the engine compartment of a car or on a cell phone tower. Others have to be extremely small for use for inside compact devices. In all cases the package designer has to consider things like materials to use to minimize stress or cracking of the die, or to account for thermal expansion and how this may affect the chip’s reliability.
The earliest technology used to connect the silicon chip to the leads inside the package was wire bonding, a low-temperature welding process. In this process, very fine wires (usually gold or aluminum, though silver and copper are also used) are bonded on one end to metal pads on the chip, and on the other end to terminals on a metal frame that has leads to the outside. The process was pioneered at Bell Labs in the 1950s, with tiny wires pressed under pressure into the chip pads at high spot temperatures. The first machines to do this became available in the late 1950s, and by the mid 1960s, ultrasonic bonding was developed as an alternative technique.
Historically this work was done in Southeast Asia because it was quite labor intensive. Since then, automated machines have been developed to do the wire bonding at very high speeds. Many other newer packaging technologies have also been developed, including one called “flip chip.” In this process, microscopic metal pillars are deposited (“bumped”) onto the pads on the chip while it’s still on the wafer, and then after testing the good die are flipped over and aligned with matched pads in a package. Then the solder is melted in a reflow process to fuse the connections. This is a good way to make thousands of connections all at once, although you have to control things carefully to make sure all of the connections are good.
Recently packaging has attracted a lot more attention. This is because of new technologies becoming available, but also new applications that are driving chip usage. Foremost is the desire to put multiple chips made with different technologies together in a single package, so called system-in-package (SiP) chips. But it’s also being driven by the desire to combine different kinds of devices, for example a 5G antenna in the same package as the radio chip, or artificial intelligence applications in which you integrate sensors with the computing chips. The big semiconductor foundries like TSMC are working with “chiplets” and “fan out packaging” as well, while Intel
Most packaging is done by third party contract manufacturers known as “outsourced assembly and test” (OSAT) companies, and the center of their world is in Asia. The largest OSAT suppliers are ASE of Taiwan, Amkor Technology
A major reason packaging has attracted attention lately is that recent Covid-19 outbreaks in Vietnam and Malaysia have contributed significantly to the worsening of the semiconductor chip supply crisis, with plant closures or reduced staffing enforced by local governments cutting off or reducing production for weeks at a time. Even if the U.S. government invests in subsidies to foster domestic semiconductor manufacturing, most of those finished chips are still going to travel to Asia for packaging, as that is where the industry and supplier networks are and where the skill base is. Thus Intel manufactures microprocessor chips in Hillsboro, Oregon or Chandler, Arizona, but it sends finished wafers to factories in Malaysia, Vietnam, or Chengdu, China for test and packaging.
Can chip packaging be established in the U.S.?
There are significant challenges to bringing chip packaging to the U.S., as most of the industry left American shores close to a half century ago. The North American share of global packaging production is only around 3%. That means the supplier networks for manufacturing equipment, chemicals (like the substrates and other materials used in packages), lead frames, and most importantly a skill base of experienced talent for the high volume part of the business haven’t existed in the U.S. for a long time. Intel just announced a $7 billion investment in a new packaging and test factory in Malaysia, though it also announced plans to invest $3.5 billion in its Rio Rancho, New Mexico operations for its Foveros technology. Amkor Technology also recently announced plans to expand capacity at Bac Ninh, Vietnam northeast of Hanoi.
A big part of this problem for the U.S. is that advanced chip packaging requires so much production experience. When you first start production, yields of good finished packaged chips will likely be low, and as you make more, you constantly improve the process and the yield gets better. Big chip customers generally won’t be willing to risk using new domestic suppliers who might take a long time to come up this yield curve. If you have a low packaging yield, you’ll be throwing away chips that would otherwise be good. Why take the chance? Thus even if we make more advanced chips in the U.S., they’ll probably still go to the Far East for packaging.
Boise, Idaho-based American Semiconductor, Inc. is taking a different approach. CEO Doug Hackler favors “viable reshoring based on viable manufacturing.” Rather than chase only high-end chip packaging like that used for advanced microprocessors or 5G chips, his strategy is to use new technology and apply it to legacy chips where there is a lot of demand, which will allow the company to practice its processes and learn. Legacy chips are much cheaper too, so yield loss isn’t as much a life-and-death issue. Hackler points out that 85% of the chips in an iPhone 11 use older technologies, for example manufactured at semiconductor nodes of 40 nm or older (which was the hot technology a decade ago). Indeed, many of the chip shortages currently plaguing the auto industry and others are for these legacy chips. At the same time, the company is trying to apply new technology and automation to the assembly steps, offering ultra-thin chip scale packaging using what it calls a semiconductor on polymer (SoP) process in which a wafer full of die is bonded to a backside polymer and then placed on a thermal transfer tape. After testing with the usual automated testers, the chips are diced on the tape carriers, and transferred to reels or other formats for high speed automated assembly. Hackler thinks this packaging should be attractive to manufacturers of Internet-of-Things (IoT) devices and wearables, two segments that could consume large volumes of chips, but aren’t as demanding on the silicon fabrication side.
What’s appealing about Hackler’s approach are two things. First, the recognition of the importance of demand to pull volume through his manufacturing line will ensure that they get a lot of practice on yield improvement. Second, they are using a new technology, and riding a technology transition is often an opportunity to unseat incumbents. New entrants don’t have the baggage of being tied to existing processes or facilities.
American Semiconductor still has a long way to go, but approaches like this will build domestic skills, and are a practical step to bringing chip packaging to the U.S. Don’t expect establishing domestic capability to be quick, but it is not a bad place to start.